Switching device

ABSTRACT

A switching device having a first and a second electronic switch connected in a half-bridge configuration and each having a control terminal for receiving a switching signal alternatively having a turn-on value and a turn-off value for taking the first and second electronic switches to an on state and to an off state, respectively; the switching device includes, for each switch, means for detecting the state of the switch and means for keeping the switching signal at the turn-off value for one of the electronic switches when the detected state of the other electronic switch is the on state.

TECHNICAL FIELD

The present invention relates to a switching device and, morespecifically, to a switching device with two switches in a half-bridgeconfiguration and means for keeping one switch in an off state when theother is in an on state.

BACKGROUND OF THE INVENTION

Switching devices are commonly used in various applications, for examplein power supply units, in oscillators, in inverters, in power amplifiersand similar. In a particular switching device, two electronic switches,typically two transistors, are connected in an half-bridgeconfiguration. Each of the two transistors is alternatively switched-onand switched-off; when one transistor is on, the other transistor is offand vice versa.

A problem in half-bridge switching devices consists of a phenomenonknown as cross-conduction. This is due to the fact that, in general, theturn-off time of the transistor which is on is higher than the turn-ontime of the transistor which is off, so that at each switching of thetwo transistors there is an interval of time in which both transistorsare on. This creates a short-circuit at the terminals of thehalf-bridge, which generates current peaks that can damage thetransistors.

In order to prevent this problem, the transistors are typicallycontrolled in a disoverlap manner, in particular, each transistor isswitched on with a preset delay, called dead time, with respect to theinstant in which the other transistor is switched off, so as to ensurethat the two transistors are never both on at the same time.

A known solution for generating a signal with a duration equal to thedead time consists in employing a transient charging (or discharging)phenomenon in a circuit including a capacitor and a resistor, or an RCcircuit, which time constant is proportional to the capacitance and theresistance of the capacitor and of the resistor, respectively. The RCcircuit is typically integrated in a chip of semiconductor materialwherein the switching device is also made; consequently, theseparameters are difficult to control with accuracy and are subject towide variations on the basis of temperature.

Consequently, the capacitor and the resistor need to be dimensioned soas to ensure that in any case the dead time is sufficiently long toprevent the two transistors from being on at the same time. Thisincreases the duration of the interval of time in which the switchingdevice is not active (with both transistors off) and does not allow theuse of the device at high switching frequencies. Additional drawbacks ofsuch structure consists in that the RC circuit is very cumbersome andoccupies a considerable area on the semiconductor chip.

A different solution consists in using a digital circuit comprising aclock signal generator, made for example by means of a quartzoscillator, which is also used to switch the two transistors; thisallows an extremely accurate dead time to be obtained. However, sincethe known clock signal generators operate with a frequency at most equalto several MHz and the duration of the on state and the off state of thetransistors is generally higher by several orders of quantities than theduration of the dead time, such a solution can only be used at ratherlow switching frequencies, for example not higher than several tens ofKHz.

SUMMARY OF THE INVENTION

The disclosed embodiments of the present invention overcome the abovementioned drawbacks with a switching device comprising a first and asecond electronic switch connected in a half-bridge configuration andeach having a control terminal for receiving a switching signalalternatively having a turn-on value and a turn-off value for taking theswitch to an on state and to an off state, respectively; the switchingdevice includes, for each switch, a circuit for detecting the state ofthe switch and a circuit for keeping the switching signal at theturn-off value when the detected state of the other switch is the onstate.

Furthermore, a corresponding method for controlling a switching deviceis also proposed.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features and the advantages of the switching device according tothe present invention will be made clear by the following description ofa preferred embodiment thereof, given purely by way of a non-restrictiveindication, with reference to the attached figures, wherein:

FIG. 1 schematically illustrates a circuit diagram of the switchingdevice;

FIG. 2 illustrates a different embodiment of the switching device.

DETAILED DESCRIPTION OF THE INVENTION

In particular, FIG. 1 illustrates a switching device 100 having twopower supply terminals 105 l and 105 h, an input terminal 105 i and anoutput terminal 105 o. Terminal 105 l is connected to a referenceterminal (or ground) and terminal 105 h is connected to the positiveterminal of a power supply source +Vcc (with a value ranging from a fewV to several hundreds of V), which negative terminal is connected to theground terminal. A general control signal Sc is applied to the inputterminal 105 i which alternatively assumes a logic value of 0, equal tothe potential of the ground terminal (0V), and a logic value of 1, equalto the potential of a signal power supply source +Vdd (for example +5V).A load LD is connected between the output terminal 105 o and the groundterminal.

The switching device 100 includes a half-bridge formed by two MOS powertransistors; in particular, a low-side N channel transistor Mnl and ahigh-side P channel transistor Mph are connected in complementarysymmetry. The source terminal of transistor Mnl is connected to thepower supply terminal 105 l, while the source terminal of transistor Mphis connected to the power supply terminal 105 h; the drain terminals oftransistors Mnl and Mph are connected together to the output terminal105 o

An auxiliary N channel MOS signal transistor Mnla (or another equivalentmeans) is associated with the transistor Mnl, which source terminal andgate terminal are connected, respectively, to the source terminal andthe gate terminal of transistor Mnl; the drain terminal of the auxiliarytransistor Mnla is connected to the positive terminal (+) of a constantcurrent generator Il, which negative terminal (−) is connected to thepositive terminal of the signal power supply source +Vdd. The currentgenerator Il prevents the formation of a short-circuit between the powersupply terminal +Vdd and the ground terminal when the auxiliarytransistor Mnla is on and is dimensioned (to provide, for example, acurrent of several tens of μA) so as to minimize power leaks in such acondition; alternatively, a current limiting resistor, or otherequivalent biasing means, is provided.

Terminal 105 i and the drain terminal of the auxiliary transistor Mnlaare connected to corresponding input terminals of an AND logic gate 110h. The output terminal of the AND logic gate 110 h is connected to theinput terminal of a voltage shift circuit (SHIFT) 115 i, which outputterminal is connected to the gate terminal of transistors Mph and Mpha.The circuit 115 i inverts the input logic signal and shifts thecorresponding voltage, variable from 0V to +Vdd, to a value included inthe range from +Vcc-Vdd and +Vcc so as to ensure that the voltagebetween the gate terminal and the source terminal of the transistors Mphand Mpha in any case assumes a correct value (this circuit consists of asimple NOT logic gate in the case in which the value of the power supplyvoltage +Vcc is essentially equal to +Vdd).

In a dual manner, a P channel MOS signal auxiliary transistor Mpha isassociated to transistor Mph, which source terminal and gate terminalare connected, respectively, to the source terminal and the gateterminal of transistor Mph; the drain terminal of auxiliary transistorMpha is connected to the negative terminal (−) of a constant currentgenerator Ih which positive terminal (+) is connected to a power supplyterminal of +Vcc-Vdd. The drain terminal of auxiliary transistor Mpha isconnected to the input terminal of a voltage shift circuit (SHIFT) 115o; the circuit 115 o shifts the input voltage, variable from +Vcc-Vddand +Vcc, to a value included in the range from 0V to +Vdd and theninverts the corresponding logic signal. Terminal 105 i is connected tothe input terminal of a NOT logic gate 120. The output terminal of theNOT gate 120 and the output terminal of the shift circuit 115 o areconnected to corresponding input terminals of an AND logic gate 110 l,which output terminal is connected to the gate terminal of transistorsMnl, Mnla.

The control signal Sc is applied directly to an input terminal of theAND gate 110 h, so that when this signal has a logic value of 0 (0V),the logic signal at its output terminal is equal to 0, regardless of thelogic signal of the other input terminal. The corresponding voltage 0V,inverted and shifted by circuit 115 i to a value of +Vcc, is applied tothe gate terminal of transistors Mph and Mpha which consequently areboth off. The voltage at the drain terminal of the auxiliary transistorMpha is consequently equal to +Vcc-Vdd and is shifted and inverted bycircuit 115 o to a value of +Vdd; the corresponding logic signal 1 isapplied to an input terminal of the AND gate 110 l so that the logicsignal 1 (control signal Sc negated by the NOT gate 120) applied to theother input terminal is sent to its output terminal. The correspondingvoltage +Vdd is applied to the gate terminal of transistors Mnl and Mnlawhich are consequently both on.

In a dual manner, when the control signal Sc has a logic value of 1(+Vdd), such a signal negated to the logic value of 0 by the NOT gate120 is sent to the output terminal of the AND gate 110 l and thecorresponding voltage 0V is applied to the gate terminal of transistorsMnl and Mnla which are consequently both off. The voltage at the drainterminal of the auxiliary transistor Mnla is consequently equal to +Vdd;the corresponding logic signal 1 is applied to an input terminal of theAND gate 110 h, so that the logic signal 1 (control signal Sc) appliedto the other input terminal is sent to its output terminal. Thecorresponding voltage +Vdd, inverted and shifted by circuit 115 i to avalue of +Vcc-Vdd, is applied to the gate terminal of transistors Mphand Mpha which are consequently both on.

As a consequence, when the control signal Sc has a logic value of 0, thetransistor Mnl is on and the transistor Mph is off, and the voltage atthe terminals of the load LD (hereafter referred to as Vo) is equal to0V; conversely, when the control signal Sc has a logic value of 1, thetransistor Mnl is off and the transistor Mph is on, and the voltage Vois equal to +Vcc. In this way, a rectangular wave form voltage isapplied to the load LD with an average value which can be adjusted byoperating on the ratio between the on time and the off time of thetransistors Mnl, Mph.

Similar considerations apply in the case in which two bipolartransistors, or other equivalent electronic switches, are connectedtogether in a half-bridge configuration with each having a controlterminal for receiving a switching signal alternatively having a turn-onvalue (+Vdd for transistor Mnl and +Vcc-Vdd for transistor Mph) and aturn-off value (0V for transistor Mnl and +Vcc for transistor Mph) fortaking the switch to an on state and to an off state, respectively.

Now, consider switching the control signal Sc from the logic value 0(transistors Mnl, Mnla on and transistors Mph, Mpha off) to the logicvalue 1. Such a logic signal is negated by the NOT gate 120 and sent tothe output terminal of the AND gate 110 l; consequently, thecorresponding voltage 0V is immediately applied to the gate terminal oftransistors Mnl and Mnla, which are consequently both switched-off aftertheir turn-off time. During this turn-off time, in which transistorsMnl, Mnla are still on, the voltage at the drain terminal of theauxiliary transistor Mnla is equal to 0V; the corresponding logic signal0 is applied to an input terminal of the AND gate 110 h and consequentlythe logic signal at its output terminal is kept equal to 0; thisinhibits the sending of the logic signal 1 (control signal Sc) appliedto the other input terminal and consequently transistors Mph and Mphaare kept off. At the end of the turn-off time of transistors Mnl andMnla, the voltage at the drain terminal of the auxiliary transistor Mnlareaches the value of +Vdd (since the auxiliary transistor Mnla is off);the corresponding logic signal 1 applied to an input terminal of the ANDgate 110 h thus enables the sending of the logic signal 1 (controlsignal Sc) applied to the other input terminal so as to switch-ontransistors Mph and Mpha (after their turn-on time).

In a dual manner, if the control signal Sc is switched from a logicvalue of 1 (transistors Mph, Mpha on and transistors Mnl, Mnla off) to alogic value of 0, such a logic signal is sent to the output terminal ofthe AND gate 110 h and then negated and shifted by the circuit 115 i tothe value of +Vcc; this voltage is immediately applied to the gateterminal of transistors Mph and Mpha, which are consequently bothturned-off after their turn-off time. During such tar-off time, thevoltage at the drain terminal of the auxiliary transistor Mpha (stillon) is equal to +Vcc and is shifted and inverted by the circuit 115 o tothe value of 0V; the corresponding logic signal 0 is applied to an inputterminal of the AND gate 110 l and then the logic signal at its outputterminal is kept equal to 0 so as to keep transistors Mnl and Mnla off.At the end of the turnoff time of transistors Mph and Mpha, the voltageat the drain terminal of the auxiliary transistor Mpha (off) reaches avalue of +Vcc-Vdd and is shifted and inverted by the circuit 115 o tothe value of +Vdd; the corresponding logic signal 1 applied to an inputterminal of the AND gate 110 l, now enables sending the logic signal 1(control signal Sc negated by the NOT gate 120) applied to the otherinput terminal so as to switch-on transistors Mnl and Mnla (after theirturn-on time).

Similar considerations apply in the case in which the NOT gate 120 isconnected to the AND gate 110 h instead of the AND gate 110 l, orequivalent logic means are used to inhibit or enable the sending of thecontrol signal Sc (for transistor Mph) or of the negated control signalSc (for transistor Mnl) according to the state of the other transistor,or more generally other equivalent means for detecting the state (on oroff) of each transistor Mnl and Mph and for keeping the switching signalapplied to the other transistor at the turn-off value (+Vcc fortransistor Mph and 0V for transistor Mnl) when the on state is detectedare provided.

The solution according to the disclosed embodiments of the presentinvention automatically adapts to the characteristics of the switchingdevice, ensuring in all conditions that the two transistors of thehalf-bridge are never on at the same time. This result is obtained bykeeping the switching device inactive only for the strictly requiredtime.

The structure of this invention is extremely simple and reliable; it canbe used in a wide range of operating frequencies of the switchingdevice. Furthermore, such structure can be easily adapted to a widevariety of requirements in terms of precision and accuracy.

The particular circuit structure described above offers the additionaladvantage of an extremely limited power loss (since it employs signalcomponents only); furthermore, it is made using a reduced number ofsimple logic gates for which reason it occupies a very limited space ofthe semiconductor chip where the switching device is typically made.

In a different embodiment of this invention illustrated in FIG. 2 (theelements corresponding to those shown in FIG. 1 are referred to with thesame numbers and symbols; explanations thereof have been omitted for thesake of simplicity), a switching device 200, including a noncomplementary half-bridge formed by two N channel MOS power transistorsMnl and Mnh, is provided. In particular, the source terminal of thetransistor Mnl is connected to the power supply terminal 105 l, whilethe drain terminal of transistor Mnh is connected to the power supplyterminal 105 h; the drain terminal of transistor Mnl and the sourceterminal of transistor Mnh are connected together to the output terminal105 o. Similar considerations apply in the case in which two P channelMOS transistors, two bipolar transistors, or similar are used.

As in the previous case, an N channel MOS signal auxiliary transistor,referred to as Mnla and Mnha, respectively, is associated to thetransistors Mnl and Mnh. A voltage shift circuit (SHIFT) 205 i isarranged between the output terminal of the AND gate 110 h and the gateterminal of transistors Mnh, Mnha; such a circuit has two power supplyterminals respectively connected to the output terminal 105 o and to abootstrap power supply terminal +Vboost having a value equal to Vo+Vdd,with Vo variable in time from a value of 0V (transistor Mnl on andtransistor Mnh off) to a value of +Vcc (transistor Mnh on and transistorMnl off). The circuit 205 i shifts the input voltage, variable from 0Vto +Vdd, to a value included in the range from Vo and +Vboost=Vo+Vdd.

In this case, the drain terminal of the auxiliary transistor Mnha isconnected to the positive terminal (+) of the constant current generatorIh, which negative terminal (−) is connected to the power supplyterminal +Vboost. An additional voltage shift circuit (SHIFT) 205 o isconnected between the drain terminal of the auxiliary transistor Mnhaand an input terminal of the AND gate 110 l; the circuit 205 o shiftsthe input voltage, variable from Vo to Vo+Vdd (with Vo variable in timefrom 0V to +Vcc) to a value in the range from 0V to +Vdd.

The operation of the switching device 200 is similar to that of thecircuit illustrated in FIG. 1, so that when the control signal Sc has alogic value of 0, the transistor Mnh is off (voltage at the gateterminal equal to Vo=0V) and the transistor Mnl is on (voltage at thegate terminal equal to +Vdd), and when the control signal Sc has a logicvalue of 1, the transistor Mnh is on (voltage at the gate terminal equalto Vo+Vdd=+Vcc+Vdd) and transistor Mnl is off (voltage at the gateterminal equal to 0V).

If the control signal Sc is switched from the logic value of 0(transistors Mnl, Mnla on and transistors Mnh, Mnha off) to the logicvalue of 1, the voltage at the gate terminal of the transistors Mnh,Mnha is kept at a value of Vo=0V for the entire turn-off time of thetransistors Mnl, Mnla, and, in a dual manner, if the control signal Scis switched from the logic value of 1 (transistors Mnh, Mnha on andtransistors Mnl, Mnla off) to a logic value of 0, the voltage at thegate terminal of the transistors Mnl, Mnla is kept at a value of 0V forthe entire turnoff time of the transistors Mnh, Mnha. This ensures thatin any condition the two transistors on the half-bridge are never on atthe same time.

Naturally, in order to satisfy local and specific requirements, a personskilled in the art may apply to the switching device described abovemany modifications and alterations all of which, however, are includedwithin the scope of protection of the invention as defined by thefollowing claims.

What is claimed is:
 1. A switching device, comprising: a first and asecond transistor connected in a half-bridge configuration, and each ofthe first and second transistors having a first and a second operatingterminal and a control terminal for receiving a switching signalalternatively having a turn-on value and a turn-off value for takingeach of the first and second transistors to an on state and to an offstate, respectively; means for each transistor for detecting the stateof the transistor and means for keeping the switching signal at theturn-off value when the state of the other transistor is the on state,the detecting means for detecting the state of the first and secondtransistors configured to output a state signal having a first and asecond logic value corresponding to the on state and to the off state ofthe first and second transistors, respectively, and including a firstand a second auxiliary transistor, respectively, each having a controlterminal, a first operating terminal and a second operating terminal,the first and second transistor and each associated auxiliary transistorhaving the control terminal and the first operating terminal in commonfor receiving the switching signal.
 2. The switching device of claim 1wherein the first transistor and the first auxiliary transistor have afirst polarity and the second transistor and the second auxiliarytransistor have a second polarity opposed to the first polarity, eachtransistor having the first terminal connectable to a correspondingpower supply source, and the first and the second transistor having thesecond terminal in common for connecting a load.
 3. The switching deviceof claim 1 wherein the first transistor, the first auxiliary transistor,the second transistor, and the second auxiliary transistor have the samepolarity, the first transistor having the first terminal and the secondtransistor having the second terminal connectable to a correspondingpower supply source, and the second terminal of the first transistor andthe first terminal of the second transistor being in common forconnecting a load.
 4. The switching device of claim 1 wherein the firsttransistor and the second transistor are power transistors and the firstauxiliary transistor and the second auxiliary transistor are signaltransistors, and wherein the second terminal of the first auxiliarytransistor is connected to first biasing means and the second terminalof the second auxiliary transistor is connected to second biasing meansand to a voltage shift circuit, the state signal consisting of a voltageto the second terminal of the first auxiliary transistor and of avoltage to the shift circuit output terminal, respectively.
 5. Theswitching device of claim 1 wherein the switching device comprises aninput terminal for receiving a general control signal alternativelyhaving the first and the second logic value, and in which the switchingsignal keeping means associated with the first switch and with thesecond switch include logic means for receiving a first input signalbeing the negated control signal and the control signal, respectively,and a second input signal being the signal output by the detecting meansassociated with the other switch, and for outputting a signal having thesecond logic value when the first and the second input signals both havethe second logic value and the first logic value otherwise, theswitching signal having the turn-off value and the turn-on value whenthe output signal has the first and the second logic value,respectively.
 6. The switching device of claim 5, wherein the first andthe second logic values are 0 and 1, respectively, the logic meansassociated with the first switch and with the second switch including afirst and a second AND logic gate, respectively.
 7. The switching deviceof claim 6, wherein the first AND gate is directly connected to thecontrol terminal of the first switch and the second AND gate isconnected via an additional voltage shift circuit to the controlterminal of the second switch for applying the corresponding switchingsignal.
 8. A half-bridge switching circuit, comprising: a firsttransistor and a second transistor coupled in series between a voltagesource and a reference voltage; and a control circuit coupled to thefirst and second transistors and configured to detect the conductionstate of the first and second transistors and to maintain one of thefirst and second transistors in a non-conducting state while the otherof the first and second transistors is in a conducting state, thecontrol circuit comprising a first auxiliary transistor coupled to thefirst transistor and to a first current source; and a second auxiliarytransistor coupled to the second transistor and to a second currentsource, the first and second auxiliary transistors configured to receivea switching signal and control the first and second transistors inresponse to the switching signal.
 9. The circuit of claim 8 wherein thecontrol circuit further comprises a first AND gate having a first inputcoupled to a switching signal source, a second input coupled to thesecond auxiliary transistor, and an output coupled to the firstauxiliary transistor; and a second AND gate having a first input coupledto the first auxiliary transistor, a second input coupled to theswitching signal source, and an output coupled to the second auxiliarytransistor.
 10. The circuit of claim 9, further comprising a firstvoltage shifter coupled in series between the output of the first ANDgate and the first auxiliary transistor; and a second voltage shiftercoupled in series between the first input of the second AND gate and thefirst auxiliary transistor.
 11. The circuit of claim 8 wherein the firstauxiliary transistor has a control terminal connected to a controlterminal of the first transistor at a first node, and wherein the secondauxiliary transistor has a control terminal connected to a controlterminal of the second transistor at a second node.
 12. The circuit ofclaim 11 wherein the control circuit further comprises a first AND gatehaving a first input coupled to a switching signal source, a secondinput coupled to a drain of the second auxiliary transistor, and anoutput coupled to the first node between the first transistor and thefirst auxiliary transistor; and a second AND gate having a first inputcoupled to the drain of the first auxiliary transistor, a second inputcoupled to the switching signal source through an inverter, and anoutput coupled to the second node between the second transistor and thesecond auxiliary transistor.
 13. The circuit of claim 12, furthercomprising a first voltage shifter coupled in series between the outputof the first AND gate and the first node between the first transistorand the first auxiliary transistor; and a second voltage shifter coupledin series between the first input of the second AND gate and the drainof the first auxiliary transistor.
 14. The circuit of claim 11 whereinthe first and second transistors and the first and second auxiliarytransistors are of the same polarity.
 15. The circuit of claim 14wherein the first voltage shifter is further coupled to a second voltagesource and to an output terminal; and wherein the second voltage shifteris further coupled to the second voltage source and to the outputterminal.
 16. A switching device, comprising: a first and a secondtransistor connected in a half-bridge configuration, each of the firstand second transistors having a control terminal for receiving aswitching signal alternatively having a turn-on value and a turn-offvalue for taking each of the first and second transistors to an on stateand to an off state, respectively; detecting means for detecting thestate of the first and second transistors and means for keeping theswitching signal at the tun-off value when the state of the othertransistor is in the on state, the detecting means configured to outputa state signal having a first and a second logic value corresponding tothe on state and to the off state of the first and second transistors,respectively; and an input terminal for receiving a general controlsignal alternatively having the first and the second logic value, and inwhich the switching signal keeping means associated with the firstswitch and with the second switch include logic means for receiving afirst input signal that is the negated control signal and the controlsignal, respectively, and a second input signal that is the signaloutput by the detecting means associated with the other switch, and foroutputting a signal having the second logic value when the first and thesecond input signals both have the second logic value and the firstlogic value otherwise, the switching signal having the turn-off valueand the turn-on value when the output signal has the first and thesecond logic value, respectively.
 17. The switching device of claim 16wherein the first and the second logic values are 0 and 1, respectively,the logic means associated with the first switch and with the secondswitch including a first and a second AND logic gate, respectively. 18.The switching device of claim 17, wherein the first AND gate is directlyconnected to the control terminal of the first switch and the second ANDgate is connected via an additional voltage shift to the controlterminal of the second switch for applying the corresponding switchingsignal.